The present invention relates generally to high speed data encoding and more particularly to encoding utilizing vector-calculated embedded-error-detection logic.
Data encoding and transmission schemes are well known to the art to provide error detection, clock recovery, and reduction of spectral components near DC. Incoming data is transformed into an encoded value for transmission. The output of the encoder may be a series of 0""s and 1""s. Decoding may recover the original incoming data along with some additional information. This additional information may include whether an incoming character contains any errors.
An error tracking scheme may be provided within the data itself. For instance, one type of error tracking scheme utilizes a running disparity. Running disparity refers to the number of 1""s in comparison to the number of 0""s of an encoded word. A running disparity is positive when there are more 1""s than 0""s. A running disparity is negative when there are more 0""s than 1""s. An equal number of 1""s and 0""s is referred to as a neutral running disparity. Data may be encoded such that a desired running disparity is maintained at specific check points. An error may be assumed on the decoding side if, after error recovery, the running disparity does not have the desired value at a specified check point.
In encoding schemes known to the art, an input word to be encoded is divided into a number of sub-blocks. A current running disparity is derived after each sub-block from the encoded sub-block data and the previous running disparity. The current running disparity, in turn, becomes the previous running disparity for the next sub-block in the current input word or first sub-block in the next input word. The previous running disparity determines the encoded value of the sub-block to which it is applied. In this process, a current running disparity must be determined after each sub-block is encoded and must be applied to the next sub-block or the next input word. Thus encoding of a sub-block may not occur until the previous sub-blocks have been encoded. As a result, the encoding of input words utilizing this process is slow.
Consequently, it would be advantageous if a data encoding scheme existed which allowed for high speed data encoding. Further, it would be advantageous to provide a data encoding scheme which could encode data while embedding error detection information simultaneously.
Accordingly, the present invention is directed to a novel system and method for encoding which may provide increased data rates while maintaining error detection, clock recovery and reduction of spectral components near DC. The present invention is further directed to an encoding scheme which may encode data while embedding error detection information simultaneously.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.